The present invention relates, in general, to the hardware-software co-design of processor-based embedded systems and more particularly, to the method for design of accelerators.
Contemporary embedded system design involving programmable components, are rapidly increasing in complexity in terms of the functionality provided and also the hardware and software components required. For example, mobile phones with integrated Wireless Application Protocol (WAP), audio, video and Personal Data Assistant (PDA) features require complicated software and hardware architectures. Such systems require the designer to provide the best performance for the lowest possible cost under the constraints of short time-to-market and flexibility for incorporation of changing standards.
System designers are under constant pressure to increase the functionality of embedded systems in order to meet the increasing demand for new applications. Design solutions need to achieve higher performance in execution time, and to simplify and modularize the design process of processor-based embedded systems. Developing new processor architectures or modifying existing ones, requires significant time and also incurs significant cost and effort. Accelerators are used as an add-on to existing designs to remove application bottlenecks, thereby obviating the need for an expensive redesign of the entire architecture of the processor-based system. This invention focuses on a method to improve the performance of existing platforms, with minimal incremental time and effort expenditure.
Design challenges in processor-based systems have been addressed in the following patents and design approaches. Before the current design methods, it is important to understand the differences between an accelerator, co-processor and application specific processor.
The application specific processor has a uniquely tailored instruction set, which is automatically derived to suit the target application. The instruction set is broad and covers a varied set of functions. The accelerator is designed to perform only a single function or a set of few functions. It does not have an instruction set with the capability to perform multiple functions in a very adaptive way. The application specific processor has to be programmed to derive the relevant application set when the application is called. Whereas, an accelerator is specifically called to execute a particular function, there is no need to program or configure it in any elaborate way. The co-processor assists the main processor by performing certain special functions. It performs the function faster than the main processor. The main processor would have executed the function in software, using its generic instruction set whereas the co-processor executes the function in predetermined hardware. The co-processor often decodes instructions in parallel with the main processor and executes only those instructions intended for it.
The thrust of the existing solutions is on optimizing the data computational task of the design process. This invention is directed to an accelerator design task comprising a data communicate and data compute task, and to an electronic design automation tool that specifically optimizes the data communicate design task using a template based approach for hardware synthesis. The template here refers to both the components and the control flow path among the components. The template consists of a configurable and programmable data communicate module and a configurable interface to a data compute module.
As the complexity of system-on-chip (SoC) devices continue to increase, the market pressures continue to dictate shorter design cycles. In the past, there was a clear demarcation between generic instruction set processors and Application Specific Integrated Circuits (ASIC). In the case of ASIC's, the algorithms are implemented for the most part in hardware. ASIC designers do not prefer to implement intensive algorithms by “running” software. In contrast, most of the SoCs have one or more instruction set processors in addition to a huge block of custom logic. Thus both the software design complexity and hardware design complexity need to be addressed simultaneously.
An approach for hardware-software co-design in processor-based systems is to use Application Specific Processors (ASP). The ASP design approach is effective when the application design lends itself to a small library of application syntaxes and predictable applications. However, it is not an efficient method for the design of processor based systems where it is difficult to predetermine radically new applications. Further, such existing solutions do not specifically focus on optimizing the communication tasks by the use of a configurable communication template.
Another approach for hardware-software co-design in processor-based systems is to focus on designer configurable computational units. Performance is enhanced by parallel processing the computational units. The present invention defines a process by which the template is optimized and also the process of customizing the control flow path for the particular application.
Another approach for hardware-software co-design in processor-based systems is to generate an integrated circuit that includes a software configurable component and a fixed hardware component. Hardware-software partitioning is approached in the context of overall processor system design. However, the thrust of the present invention is on using the partitioning approach in the communication module.
Still another approach for hardware-software co-design in processor-based systems involves electronic design using a library of programmable co-processors. This broad approach can be used in applications where limited configurability is expected, typically in applications requiring minimum design upgrades. However, in the design of complex applications with decreasing design cycle times, it is difficult to anticipate all the co-processor blocks that will be required. The customizable feature of the present invention's template is an improvement over the prior art.
The market therefore requires an optimized design solution for the communication components and the data path in the accelerators and co-processors. The “optimized design solution” herein refers not only to a faster and less complex method of design, but also to improved cycle time performance.